1. Technical Field
The present invention relates to a clock control circuit and a clock control method which switchingly supply a high-speed clock and a low-speed clock in accordance with the operational state of a system LSI.
2. Description of the Related Art
For example, Japanese Patent Application Laid-Open (JP-A) No. 10-145446 discloses a clock control section which, in order to reduce the consumption of electric power at a portable terminal, stops an operation clock, which is supplied to a central processing unit (hereinafter, “CPU”), at times when processing at the CPU is not required.
The clock control section is structured by an oscillation stopping/restoring control circuit which controls the starting and stopping of the oscillation of an oscillation circuit; a clock supply control circuit controlling whether or not a clock signal outputted from the oscillation circuit is to be outputted to a CPU; and a stable oscillation timer which is activated by an interrupt signal and counts low frequency clock signals. When the count value reaches a given value, the stable oscillation timer outputs a control signal to the clock supply control circuit in order for a clock signal to be outputted to the CPU.
At such a portable terminal, when processing by the CPU is completed, a control signal for stopping the oscillation circuit is outputted from the CPU to the oscillation stopping/restoring control circuit. In this way, the high-speed operation clock generated by the oscillation circuit is stopped, and the electric power consumed at the oscillation circuit and the CPU is reduced. During this time, a low frequency clock oscillator, a timer circuit, a receiving circuit, and the like continue to operate. When a predetermined period of time has passed or when a control signal is received from a base station or the like, an interrupt signal is outputted and is supplied to the oscillation stopping/restoring control circuit and the stable oscillation timer.
When the interrupt signal is supplied to the oscillation stopping/restoring control circuit, the oscillation stopping/restoring control circuit instructs the oscillation circuit to begin oscillation. On the other hand, the stable oscillation timer starts counting of a low frequency clock signal. Then, when the count value of the stable oscillation timer reaches a given value, a control signal for making the clock signal of the oscillation circuit be outputted to the CPU is outputted from the stable oscillation timer to the clock supply control circuit. In this way, the clock signal of the oscillation circuit, whose oscillation operation has stabilized after a predetermined period of time has elapsed, is supplied to the CPU.
However, a portable terminal equipped with a conventional clock control section has the following problems.
When processing at the CPU is completed, the clock signal for the CPU is completely stopped, and the mode proceeds to a standby mode. However, even during this standby mode, operation of the timer circuit, the receiving circuit, and the like must continue. Therefore, the timer circuit and the receiving circuit must be structured so as to operate completely independently of operation of the CPU. A problem arises in that there is the concern that the circuit structure will become complex.